Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results include a variety of components that communicate with each other via a communication bus such as a peripheral component interconnect (PCI) bus.
Typically a bus consists of several lines of electrically conductive material. The bus permits electrical signals representing data and control instructions to be readily transmitted between different components coupled to the bus. The order and speed of which the components interact with one another over the bus has a substantial impact on the performance of the computer system. For example, much of a computer systems functionality and utility is realized through the use of components referred as peripheral devices. Frequently the speed at which peripheral devices interact with the rest of the computer system is critical. For many peripheral devices, such as graphics adapters, full motion video adapters, small computer system interface (SCSI) host bust adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. For example, the speed at which a graphics adapter can communicate its responses is a major factor in the computer systems usefulness as an entertainment device. Hence the rate at which data can be transferred among various peripheral devices often determines whether the computer systems is suited for a particular purpose.
In order to maximize the benefits of electronic systems such as computers, the electronics industry has engaged in activities to develop several types a progressively faster bus architectures. Recently, the PCI bus architecture was developed to provide a high-speed, low latency bus architecture from which a larger variety of computer systems could be developed. As the number of applications which computers are used increases so does the demand for even greater bus performance capabilities. The bandwidth of a bus has a significant impact on its performance capabilities. Bandwidth is the amount of information communicated over the bus in a particular amount time. One way of increasing bandwidth is to change the configuration of the bus and components coupled to the bus. For example, increasing the number of bus lines that carry communication signals increases the bandwidth and thus over time the width or number of lines in a typical bus has increased.
These changes in bus and component configurations do not typically occur instantaneously for all components of a system and most systems are implemented with a degree of "backward" compatibility. In particular, changes in the configuration of devices coupled to a bus often lag behind configuration changes in the bus itself. For example, when PCI 2.1 specification standards were implemented to a take advantage of a wider 64-bit bus architecture many systems still relied upon 32 bit peripheral components resulting in a mixture of 64-bit and 32-bit masters (initiators) and slaves (targets) coupled to the same bus. Therefore, PCI 2.1 specification requires that 64 bit bus architectures maintain backward compatibility for 32-bit devices. This forces a 64-bit initiator to resolve the target configuration type (e.g., 32-bit or 64-bit) and frame#/irdy# signal resolution (in single transfers) before the 64-bit initiator proceeds with a data transfer. Apart from resolving the target type in a 64-bit environment, framing resolution is required whenever the initiator requests single 64-bit transfers. Framing resolution can take one clock to complete (e.g., when there is a 64-bit target) or multiple clocks to complete (e.g., when there is a 32-bit target).
In a typical multi configuration environment there is a target configuration recognition protocol that a master component engages in to determine the configuration of a slave component. For example in a 64-bit PCI environment the initiator accesses the bus searching for potential 64-bit targets and engages in a target configuration recognition protocol. Configuration determination handshaking occurs at the beginning of a transaction before a data transfer begins and therefore often delays communication of useful information between an initiator and a target. These configuration-determination delays increase the latency of communications on the bus and hence reduces the throughput. There is an initial configuration-determination latency in which clock cycles are expended determining what type of transfers are possible (e.g., whether a 32 bit or 64 bit transfer is possible). These clock cycles determining what type of transfers are possible are not available for primary data transfer activity (and are essentially wasted). In PCI bus architectures in which the configuration determination handshaking begins in a 64 bit configuration the power consumption is also increased due to switching of information from the upper 64 bit data lines to the lower 32 bit data lines for communications that involve 32-bit targets.
What is required is a system and method that minimizes communication delays due to configuration determination protocols in bus architectures that include a variety of initiator and target configurations. The number of overall clock cycles required to achieve primary data throughput should be decreased by providing an efficient and effective reduction of clock cycles expended on handshaking required to determine the configuration of a target. The system and method should reduce power consumption associated with switching of information from upper 64 bit PCI data lines to lower 32 bit PCI data lines for communications that involve 32-bit targets.